CPUClock

Module information



Overview


Modern ARM hardware has the ability to operate over a range of preset clock speeds (and voltage). Heat and power drain can be reduced by using a lower clock speed and voltage, at the expense of slower processing. The RISC OS operating system is able to switch clock speeds 'on the fly'. This means that the clock speed can be reduced during periods of low activity, and switched up when more processing is occurring. However, running the cpu hard will result in a rise in temperature of the cpu. Particularly during periods of high ambient temperature and poor case ventilation this rise can be substantial. See the CPUClock user guide for a fuller description of how RISC OS switches cpu speed.

The CPUClock module implements a means of monitoring the cpu die temperature. A temperature control mode is available which will automatically reduce the cpu clock speed if the temperature of the cpu rises during periods of high load. The trigger temperature is user definable. When the temperature has fallen sufficiently, the cpu fast clock speed will be reset to its higher value.

Since the core functionality is in the module, the control feature will continue to operate even if the wimp enters a non-multitasking period.

Applications, other than the CPUClock front end itself, can interact with the module, setting the operating parameters, and reading back data by means of a SWI interface. The available SWI calls are detailed below. One caveat - if more than one application is trying to control the module at the same time, the module may end up in a state different to that which a particular application expects it to be in.


SWI calls


CPUClock_ReadTemperature
(SWI &59980)

Returns current cpu temperature and clock speed.

On entry

--

On exit

The current die temperature and current fast speed are returned.

R0 = current cpu die temperature in deg C
R1 = Flags
bit 0 set - auto-control enabled
bit 1 set - returned temperature is a running average
bit 2 set - cpu fast speed has been reduced
bits 3-4 - 2 bit number - temperature level with respect to the set limits
Value = 0 - temperature is below lower limit
Value = 1 - temperature is between lower and upper limit
Value = 2 - temperature is above upper limit
Value = 3 - reserved
bit 5 set - IRQs will be enabled during callback
bit 6 set - Raspberry Pi hardware so fan control will be available
bit 7 set - fan control is enabled
bit 8 set - fan is on
All other bits reserved.
R2 = current fast speed index
R3 = current fast speed in MHz
R4 = cpu die temperature in tenth of a deg kelvin
R5 = cpu die temperature in tenth of a deg C

CPUClock_SetTemperatureLimits
(SWI &59981)

Sets the cpu temperature limits to be used for control.

On entry
R0 = Upper temperature limit (in deg C)
R1 = Lower temperature limit (in deg C)

If R0 = 0 on entry, no change is made, but previous limits in force are returned

On exit

The previous limits in force are returned.

R0 = Previous upper temperature limit (in deg C)
R1 = Previous lower temperature limit (in deg C)

CPUClock_ModuleInfo
(SWI &59982)

Returns various information about the state of the module.

On entry
---
On exit

Returns the following information.

R0 = module version number * 100, i.e. version 1.03 would be returned as 103
R1 = Flags
bit 0 set - auto control enabled
bit 1 set - temperature is a running average
bit 5 set - IRQs will be enabled during callback
bit 6 set - Raspberry Pi hardware so fan control will be available
bit 7 set - fan control is enabled
All other bits reserved.
R2 = call every delay in cs
R3 = Upper temperature limit (in deg C)
R4 = Lower temperature limit (in deg C)
R5 = Statistics accumulation time
R6 = Fan related temperatures
Bits 0-7: Fan turn on temperature
Bits 8-15: Fan turn off temperature

CPUClock_SetControlMode
(SWI &59983)

Turns temperature control on or off.

On entry
R0 = New auto-control state.
Bit 0 = 0 - set auto control off
Bit 0 = 1 - set auto control on
On exit
R0 is preserved

CPUClock_SetAverageMode
(SWI &59984)

Turns temperature averaging on or off.

On entry
R0 = New temperature averaging state.
Bit 0 = 0 - set temperature averaging off
Bit 0 = 1 - set temperature averaging on
On exit
R0 is preserved

CPUClock_SetTemperatureReadTime
(SWI &59985)

Sets the interval between each read of the die temperature..

On entry
R0 = new interval time in centiseconds

The upper and lower values allowed are limited internally. The minimum time allowed is 40 cs. The maximum time allowed is 300 cs.

On exit
R0 is preserved

CPUClock_NewSpeedSet
(SWI &59986)

Used by an application to inform the module that a new default fast speed has been set.

On entry
R0 = Flags
Bit 0 = 0 - the speeds are expressed as the speed index
Bit 0 = 1 - the speeds are expressed in MHz
R1 = New fast speed
R2 = New slow speed
On exit
R0, R1, R2 are preserved

CPUClock_HardwareInfo
(SWI &59987)

Returns some information about the hardware. Subject to change.

On entry
---
On exit
R0 = Number of available speeds
R1 = Minimum speed available in MHz
R2 = Maximum speed available in MHz

CPUClock_StatusSummary
(SWI &059988)

The module keeps statistics about the temperature variation of the cpu and any throttling applied during the configured time period. Use CPUClock_StatisticsOp with reason codes 1 or 2 to set the time period.

On entry
---
On exit
R0 = CPU temperature (in deg C) averaged over the configured time period
R1 = Lowest CPU temperature (in deg C) during the configured time period
R2 = Highest CPU temperature (in deg C) during the configured time period
R3 = Fraction of the time (in per cent) the fast cpu speed was in a reduced state during the configured time period

CPUClock_StatisticsOp
(SWI &059989)

This SWI allows a number of actions related to the collection of temperature statistics to be carried out. The particular action is determined by the reason code in R0 on entry.

On entry
R0 = reason code
Other registers depend on reason code
On exit
R0 may be corrupted
Other registers depend on reason code

Reason codes

R0Action
0Statistics enable/disable
1Set accumulation time by index
2Set accumulation time by value
3Reset accumulated values to zero
4Return addresses of the accumulated arrays
5Return defined settings

For details of each of these reason codes, see below.


CPUClock_StatisticsOp 0
(SWI &059989)

Turns statistics accumulation on or off.

On entry
R0 = 0 (reason code 0)
R1 = accumulation state
Bit 0 = 0 - set statistics accumulation off
Bit 0 = 1 - set statistics accumulation on
On exit
R0 is preserved

CPUClock_StatisticsOp 1
(SWI &059989)

Sets the time period over which each measurement of the maximum and minimum CPU temperatures is taken by index. The module holds a default set of times, and the value in R1 is used as an index in to this array. The value is checked and limited to valid values. It is possible to obtain the default values using CPUClock_StatisticsOp 5. In module version 0.06 they range from 500 - 6000 cs (5 - 60 s).

On entry
R0 = 1 (reason code 1)
R1 = index for time period
On exit
R0 is preserved
R1 = previous index value

If R1 = -1 on entry, the current index value is returned in R1 without any change being made.


CPUClock_StatisticsOp 2
(SWI &059989)

Sets the time period over which each measurement of the maximum and minimum CPU temperatures is taken by value in units of centiseconds. The value is checked and limited to values within the default range. It is possible to obtain the default values using CPUClock_StatisticsOp 5.

On entry
R0 = 2 (reason code 2)
R1 = time period in cs
On exit
R0 is preserved
R1 = previous time period in cs

If R1 = -1 on entry, the current time period is returned in R1 without any change being made.


CPUClock_StatisticsOp 3
(SWI &059989)

This op will clear the values stored in the arrays of raw, maximum and minimum temperatures, setting all counts to zero.

On entry
R0 = 3 (reason code 3)
On exit
---

CPUClock_StatisticsOp 4
(SWI &059989)

Returns the addresses of the arrays for the raw, minimum, and maximum temperatures. These addresses will be required to read the data.

On entry
R0 = 4 (reason code 4)
On exit
R0 = address of the maximum temperature array
R1 = address of the minimum temperature array
R2 = address of the raw temperature data array

CPUClock_StatisticsOp 5
(SWI &059989)

Returns various settings and preset values used in the accumulation of the cpu temperature statistics. These are compiled in to CPUClock front end and module but this reason code provides a means for other apps to read these values from the module.

On entry
R0 = 5 (reason code 5)
On exit
R0bit 0 set if statistics collection is enabled
R1number of default accumulation times
R2address of the default accumulation times data array
R3bits 0-7 contains the minimum temperature used in the statistical accumulation
bits 8-15 contains the upper temperature used in the statistical accumulation
Note: If the CPU temperature falls below the minimum temperature, it will be counted as being at the minimum temperature. If the CPU temperature rises above the maximum temperature, it will be counted as being at the maximum temperature.
R4Number of slots used for the histogram data.

CPUClock_MiscOp
(SWI &05998A)

This SWI allows a number of miscellaneous actions to be carried out. The particular action is determined by the reason code in R0 on entry.

On entry
R0 = reason code
Other registers depend on reason code
On exit
R0 may be corrupted
Other registers depend on reason code

Reason codes

R0Action
0Enable or disable IRQs during callback

For details of each of these reason codes, see below.


CPUClock_MiscOp 0
(SWI &05998A)

Enables/disables IRQs during callback.

On entry
R0 = 0 (reason code 0)
R1 = IRQs enable state
Bit 0 = 0 - IRQs will not be enabled during callback
Bit 0 = 1 - IRQs will be enabled during callback
On exit
R0 is preserved

CPUClock_SetFanControl
(SWI &5998B)

Set up fan control behaviour. Subject to change.

On entry
R0 = Fan control mode
R0 = 0 - Fan control disabled
R0 = 1 - Fan control enabled
R1 = Fan trigger on temperature
R2 = Fan trigger temperature differential
On exit
Details to be finalised


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CPUClock is © Chris Johnson, 2012
Email:chris@chris-johnson.org.uk